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dsPIC30F4011/4012

DS70135G-page 156

2010 Microchip Technology Inc.

21.2.7

FAIL-SAFE CLOCK MONITOR

The Fail-Safe Clock Monitor (FSCM) allows the device

to continue to operate even in the event of an oscillator

failure. The FSCM function is enabled by appropriately

programming the FCKSM<1:0> Configuration bits

(Clock Switch and Monitor Selection bits) in the FOSC

device Configuration register. If the FSCM function is

enabled, the LPRC internal oscillator runs at all times

(except during Sleep mode) and is not subject to

control by the SWDTEN bit.

In the event of an oscillator failure, the FSCM

generates a clock failure trap event and switches the

system clock over to the FRC oscillator. The user then

has the option to either attempt to restart the oscillator

or execute a controlled shutdown. The user may decide

to treat the trap as a warm Reset by simply loading the

Reset address into the oscillator fail trap vector. In this

event, the CF (Clock Fail) status bit (OSCCON<3>) is

also set whenever a clock failure is recognized.

In the event of a clock failure, the WDT is unaffected

and continues to run on the LPRC clock.

If the oscillator has a very slow start-up time coming

out of POR, BOR or Sleep, it is possible that the

PWRT timer will expire before the oscillator has

started. In such cases, the FSCM is activated. The

FSCM

initiates

clock

failure

trap,

and

the

COSC<1:0> bits are loaded with the Fast RC (FRC)

oscillator selection. This effectively shuts off the

original oscillator that was trying to start.

The user may detect this situation and restart the

oscillator in the clock fail trap Interrupt Service Routine

(ISR).

Upon a clock failure detection, the FSCM module

initiates a clock switch to the FRC oscillator as follows:

The COSC<1:0> bits (OSCCON<13:12>) are

loaded with the FRC oscillator selection value.

CF bit is set (OSCCON<3>).

OSWEN control bit (OSCCON<0>) is cleared.

For the purpose of clock switching, the clock sources

are sectioned into four groups:

Primary

Secondary

Internal FRC

Internal LPRC

The user can switch between these functional groups

but cannot switch between options within a group. If the

primary group is selected, then the choice within the

group

always

determined

the

FPR<3:0>

Configuration bits.

The OSCCON register holds the control and status bits

related to clock switching.

COSC<1:0>: Read-only status bits always reflect

the current oscillator group in effect.

NOSC<1:0>: Control bits which are written to

indicate the new oscillator group of choice.

- On POR and BOR, COSC<1:0> and

NOSC<1:0> are both loaded with the

Configuration bit values, FOS<1:0>.

LOCK: The LOCK status bit indicates a PLL lock.

CF: Read-only status bit indicating if a clock fail

detect has occurred.

OSWEN: Control bit changes from a ‘0’ to a ‘1’

when a clock transition sequence is initiated.

Clearing the OSWEN control bit aborts a clock

transition in progress (used for hang-up

situations).

If Configuration bits, FCKSM<1:0> = 1x, then the clock

switching and Fail-Safe Clock Monitor functions are

disabled. This is the default Configuration bit setting.

If clock switching is disabled, then the FOS<1:0> and

FPR<3:0> bits directly control the oscillator selection,

and the COSC<1:0> bits do not control the clock

selection. However, these bits do reflect the clock

source selection.

21.2.8

PROTECTION AGAINST

ACCIDENTAL WRITES TO OSCCON

A write to the OSCCON register is intentionally made

difficult because it controls clock switching and clock

scaling.

To write to the OSCCON low byte, the following code

sequence must be executed without any other

instructions in between:

Byte Write 0x46 to OSCCON low

Byte Write 0x57 to OSCCON low

Byte Write is allowed for one instruction cycle. Write the

desired value or use bit manipulation instruction.

To write to the OSCCON high byte, the following

instructions must be executed without any other

instructions in between:

Byte Write 0x78 to OSCCON high

Byte Write 0x9A to OSCCON high

Byte Write is allowed for one instruction cycle. Write the

desired value or use bit manipulation instruction.

Note:

The application should not attempt to

switch to a clock of frequency lower than

100 kHz when the Fail-Safe Clock Monitor

is enabled. If such clock switching is

performed, the device may generate an

oscillator fail trap and switch to the Fast

RC (FRC) oscillator.

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